1. Field of the Invention
Embodiments of the present invention relate to a current mode output driver of a semiconductor memory device for adjusting an output current using a gate voltage and a method for adjusting an output current using the current mode output driver.
This application claims the priority of Korean Patent Application No. 2003-32556, filed on May 22, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
FIG. 1 shows a general data input/output interface of a semiconductor memory device, such as a rambus DRAM (hereinafter, referred to as ‘RDRAM’). In FIG. 1, the plurality of memory devices 13 are connected to the chipset 11 through the transmission line 12. One end of the transmission line 12 is single-terminated by the terminating resistor Rterm and the terminating voltage Vterm.
Each of the plurality of memory devices 13 includes a current mode output driver for outputting data read from a memory outside the memory device 13. The current mode output driver has a large resistance both when it is turned on and when it is turned off, which facilitates impedance matching. Therefore, the current mode output driver is beneficial in RDRAM. The current mode output driver can also be used in systems for connecting chips to each other.
If the current mode output driver is a NMOS transistor, the voltage level at the gate terminal of the NMOS transistor is according to a data value read from the memory core. A drain current is generated from the NMOS transistor according to the voltage level at the gate terminal. This drain current is propagated through a channel or a wire. Since it is desirable for the current mode output driver to have a very large output resistance when it is in an on state, the NMOS transistor operates in saturation. Accordingly, the NMOS transistor should maintain a condition of “gate voltage (Vg)<drain voltage (Vd)+threshold voltage (Vt)”.
If an internal voltage VDD is applied to the gate of the NMOS transistor and a lower voltage is generated at the drain of the NMOS transistor, the condition of “gate voltage (Vg)<drain voltage (Vd)+threshold voltage (Vt)” can not be maintained. Accordingly, the output resistance of the current mode output driver is significantly reduced. Accordingly, if the current mode output driver is a single NMOS transistor, it is preferable that an appropriate voltage VA with a value between the internal voltage VDD and the threshold voltage Vt is used as the gate voltage of the NMOS transistor. However, since the voltage VA having a large current supply ability should be generated inside the chip, an increase of chip area and current consumption occurs. Accordingly, various semiconductor devices, as well as RDRAM, use a stacked driver. A current mode output driver implemented by such a stacked driver is disclosed in U.S. Pat. No. 6,556,049.
FIG. 2 is a circuit diagram of a current mode output driver, wherein the current mode output driver is used for a RDRAM. The current mode output driver 30 is connected to a transmission line 20 and generates a predetermined output voltage Vout on a node NODE according to data values. The current mode output driver 30 includes a driver circuit 40 and a bias circuit 50. The driver circuit 40 includes a plurality of driver segments 41 through 47 and the bias circuit 50 includes a plurality of bias circuits 51 through 57.
The plurality of bias circuits 51 through 57 output enable signals ENVG0 through ENVG6, respectively, to the plurality of driver segments 41 through 47, in response to received current control signals CC0 through CC6. Each of the current control signals CC0 through CC6 includes a predetermined number of bits. Each of the plurality of driver segments 41 through 47 includes 2n stacked drivers, wherein n is a positive integer. The number of the stacked drivers included in each of the plurality of driver segments 41 through 47 are different. For example, the driver segment 41 includes a single driver, the driver segment 42 includes two drivers, and the driver segment 43 includes four drivers. Likewise, the number of the drivers included the driver segments 44 through 47 each respectively corresponds to 2n and therefore the final driver segment 47 includes sixty-four drivers.
Each driver includes NMOS transistors N1 and N2. The source of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2. The drain of the NMOS transistor N1 is connected to the node NODE. The enable signals ENVG0 through ENVG6 are input into the gate of the NMOS transistor N1. The source of the NMOS transistor N2 is connected to ground. Data DATA read from a memory core is input to the gate of NMOS transistor N2. The same enable signal is input into the gates of each the NMOS transistors N1 for a given driver segment. For example, the enable signal ENVG0 is input to the gate of one NMOS transistor N1 in the driver segment 41, while the enable signal ENVG1 is input into the gates of two NMOS transistors N1 in the driver segment 42. Likewise, the enable signal ENVG2 is input into four gates of the NMOS transistors N1 in the driver segment 43 and the enable signal ENVG6 is input into sixty-four gates of the NMOS transistors N1 in the driver segment 47.
The stacked driver of FIG. 2 has a large output resistance. The large output resistance is due to the NMOS transistors N1 operating in saturation, although the NMOS transistors N2 operates in a linearly and has a small resistance when data DATA of 1, (i.e. an internal voltage VDD) is inputted to the gate of the NMOS transistor N2. Since the enable signals ENVG0 through ENVG6 input into the gates of the NMOS transistors N1, have lower voltage levels than the internal voltage level VDD, the NMOS transistors N1 operate in saturation.
Each of the plurality of bias circuits 51 through 57 include the transmission gate 61 and the NMOS transistor N11. The drain of the NMOS transistor N11 is connected to an output terminal of the transmission gate 61. The source of the NMOS transistor N11 is connected to ground VSS. The current control signals CC0 through CC6 are input to the transmission gate 61. The opposite of CC0 through CC6 (CC0B through CC6B) are input into the gate of the NMOS transistor N11. The transmission gate 61 is turned on or off according to the current control signals CC0 through CC6. The transmission gate 61 receives a predetermined gate voltage Vg and outputs the gate voltage Vg as the enable signals ENVG0 through ENVG6 to an output terminal when it is turned on.
The NMOS transistor N11 is also turned on or off according to the current control signals CC0 through CC6. The NMOS transistor N11 is turned on when the transmission gate 61 is turned off, and outputs the ground voltage as the enable signal ENVG0 through ENVG6 to a drain terminal. The voltages of the enable signals ENVG0 through ENVG6 reaches the level of the gate voltage Vg or the level of the ground voltage VSS, in response to the current control signals CC0 through CC6. Accordingly, the NMOS transistors N1 in the plurality of driver segments 41 through 47 are turned on or off, according to the voltage levels of the enable signals ENVG0 through ENVG6.
The current mode output driver 30 allows a predetermined level of output current Iout to flow, so that a channel impedance matching condition of the transmission line 20 is satisfied, regardless of changes in temperature or voltage. Accordingly, the current mode output driver 30 checks the output current Iout continuously and adjusts the output current value Iout to maintain a constant current value. For example, in a RDRAM, when the current mode output driver 30 allows an output current Iout of 28.57 mA to flow and an output voltage Vout is varied between 1.8 V to 1.0 V by the output current Iout. The current mode output driver 30 checks whether the output voltage Vout is higher or lower than 1.0 V, and adjust the amount of the output current Iout.
The level of the output current Iout is controlled by the current control signals CC0 through CC6. For example, if the output voltage Vout is higher than 1.0 V, (i.e. the output current Iout is smaller than 28.57 mA), it is necessary to increase the value of the current control signals CC0 through CC6 by one bit. Likewise, if the output voltage Vout is lower than 1.0 V (i.e. the output current Iout is larger than 28.57 mA), it is necessary to reduce the value of the current control signal CC0 through CC6 by one bit. As the value of the current control signal CC0 through CC6 is changed, the voltage level of the enable signals ENVG0 through ENVG6 are also changed, controlling the number of the driver segments 41 through 47 turned on. As a result, the amount of the output current Iout is controlled.
In the RDRAM of FIG. 2, current control signals consist of seven bits and a current with 27 (i.e., 128) levels are generated by the current control signal. For example, if it is assumed that a current control signal is ‘1001011’, only the enable signals ENVG6, ENVG3, ENVG1, and ENVG0 reach the gate voltage Vg and the remaining enable signals ENVG2, ENVG4, and ENVG5 reach the ground voltage VSS. As a result, only the driver segments 47, 44 (not shown), 42, and 41 corresponding to 26, 23, 21, and 20 among seven driver segments 41 through 47 divided according to a ratio of 26:25:24:23:22:21:20 are turned on, to output data DATA. In other words, only 75 drivers among the whole 127 drivers are turned on. In the method that adjusts the amount of the output current Iout by changing the number of the driver segments 41 through 47 turned on or off, the amount of the output current Iout is proportional to a value of the current control signal CC0 through CC6.
FIG. 3 is a plot showing a relationship between a value of a current control signal and an output current. In FIG. 3, reference symbols A, B, and C represent current control signals classified according to their bit numbers. In other words, the bit number of the current control signal in the case of C is larger than the current control signal in a case of B. Also, the bit number of the current control signal in the case of B is larger than the current control signal in the case of A. For example, the bit number of the current control signal can be seven in the case of A, eight in the case of B, and nine in the case of C. As it goes from the case A to the case C, resolution of the output current Iout increases. In FIG. 3, an amount of current adjusted by one driver is Itotal/127, which corresponds to resolution of the output current Iout. When one driver is turned on or off, the amount of output current Iout is changed by Itotal/127. In FIG. 3, resolutions of the output currents Iout for the cases A through C are Itotal3/127, Itotal2/127, and Itotal1/127, respectively.
The current mode output driver 30 includes a bias circuit (e.g. bias circuits 51 through 57) and a signal line for supplying the enable signals ENVG0 through ENVG6 to each of the plurality of driver segments 41 through 47. Since the number of the current mode output drivers 30 included in one memory device is the same as the number of data input/output pins, signal lines corresponding to the number of the enable signals ENVG0 through ENVG6 must be wired to each of the driver segments of the plurality of current mode output drivers. Also, since the signal lines must be located with predetermined intervals from one another and relatively large capacitors must be connected to the signal lines in order to supply the enable signals ENVG1 through ENVG6 (each having a fine analog voltage), many difficulties exist in circuit design. Accordingly, since the current mode output driver 30 includes as many signal lines and bias circuits as the number of the enable signals ENVG0 through ENVG6, it occupies a very large area within a semiconductor chip. When increasing the bit number of the current control signal in order to increase resolution of the output current Iout, the current mode output driver 30 must include additional signal lines, bias circuits, and driver segments, which further increases the occupied area of the current mode output driver within the semiconductor chip.